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ICs for Communications
Four Channel Codec Filter with PCM- and -Controller Interface SICOFI(R)4-C PEB 2466 Version 1.2
Data Sheet 02.97
DS 2
Edition 02.97 This edition was realized using the software system FrameMaker(R). Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-
PEB 2466 Revision History: Previous Versions:
Current Version: 02.97 Preliminary Data Sheet 05.95 Errata Sheet 08.95 (valid) for V1.1) Errata Sheet 05.96 (valid for V1.2) Preliminary Data Sheet 03.96 Data Sheet 06/96
Last Revision Page (in last revision) 1 2-4 5-8
Subjects (major changes regarding Preliminary Data Sheet 03.96) Featurelist updated Chapter "Major Applications" added Errors in pin configuration fixed Values of filter and coupling capacitors fixed Several minor clarifications PCM interface clarified Byte by byte transfer with the C-interface added Types of Commands and Databytes clarified Several errors in programming examples fixed IM-Filter changed to IM/R1-filter CRAM architecture described Error in definition of XR4-register fixed Error in definition of XR5-register fixed Definition of "crash" added Figure for "setting slopes in XR6" added Chapter about programmable filters updated Chapter about "QSICOS" added Clear separation of A-law and -law ICN-spec updated Values for power dissipation and current-consumption updated Values for analog input and output resistance updated Figure for selection of optimum coupling cap. added Timing spec. figures for digital interfaces added, times updated Description of Level Metering function added Guidelines for Boarddesign added
12-15 17 18 19-23 25 32 38 39 39 41 45-46 46-47 48 49 58 59 60 61-64 65 68
PEB 2466 Revision History: Previous Versions:
Current Version: 02.97 Preliminary Data Sheet 05.95 Errata Sheet 08.95 (valid for V1.1) Errata Sheet 05.96 (valid for V1.2) Preliminary Data Sheet 03.96 Data Sheet 06.96
Last Revision Page (in current version) 4 26 27 39 42 44 45 46 57 58 63 64 65 66 5, 6, 58
Subjects (major changes since last revision)
Footnote added to the pins VDDA12 and VDDA34, reference added to footnote for filter-capacitors clarification, INT12, INT34 are active high AX1 and AX2 exchanged, in figure "CUT OFFs" and Loops Footnote added regarding attenuation of HPR and HPX Figure "Setting of Slopes in Register XR6" updated Errors in description "Standby- and Operating mode" fixed (PU bit, CR1) Figure in chapter "QSICOS" clarified Hint for tool "QSUCCONV.EXE" added Test conditions completed "Analog output load"-spec added Change for clarification, Rout -> Rload Figure updated (AX1 and AX2 exchanged) Command description updated Figure "Proposed Test Circuit" updated Layout-figure updated Coupling capacitors in transmit direction updated to 39 nF
PEB 2466
Table of Contents 1 1.1 1.2 1.3 2 2.1 2.2 2.3 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.4 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 3.5.7 3.5.8 3.5.9 3.6 3.6.1 3.6.2 3.6.3 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7
Page
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 SICOFI(R)-4-C Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 The PCM-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 The -Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Programming the SICOFI(R)-4-C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Types of Command and Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Examples for SICOFI(R)-4 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 SOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 CR0 Configuration Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 CR1 Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 CR2 Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 CR3 Configuration Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 CR4 Configuration Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 CR5 Configuration Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 COP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 XOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 XR0 Extended Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 XR1 Extended Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 XR2 Extended Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 XR3 Extended Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 XR4 Extended Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 XR5 Extended Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 XR6 Extended Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 XR7 Extended Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Setting of Slopes in Register XR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 The Signaling Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Programmable Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 QSICOS Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Transmission Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Out-of-Band Signals at Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Out-of-Band Signals at Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Out of Band Idle Channel Noise at Analog Output . . . . . . . . . . . . . . . . . . . . .62 Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Gain Tracking (receive or transmit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
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PEB 2466
Table of Contents 4.8 4.8.1 4.8.2 4.9 4.10 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 6 7 7.1 7.2 8 9 9.1 9.2 9.3
Page
Total Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Total Distortion Measured with Sine Wave . . . . . . . . . . . . . . . . . . . . . . . . . .65 Total Distortion Measured with Noise According to CCITT . . . . . . . . . . . . . .66 Single Frequency Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Transhybrid Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Coupling Capacitors at the Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . .71 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 PCM-Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 -Controller Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Signaling Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 From the C-interface to the SO/SB-pins (data downstream) . . . . . . . . . . . .75 From the SI/SB-pins to the C-interface (data upstream) . . . . . . . . . . . . . . .75 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Level Metering Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Programming the SICOFI(R)-4-C Tone Generators . . . . . . . . . . . . . . . . . . . .79 Proposed Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Guidelines for Board-Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Board Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Filter Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Example of a PEB 2466-board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
IOM(R), IOM(R)-1, IOM(R)-2, SICOFI(R), SICOFI(R)-2, SICOFI(R)-4 and SICOFI(R)-4C, are registered trademarks of Siemens AG.
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PEB 2466
General Description 1 General Description
The four channel Signal Processing Codec Filter PEB 2466 SICOFI-4-C is the logical continuation of a well established family of SIEMENS programmable codec-filter-ICs. Its major difference to the PEB 2465 (SICOFI-4) is the PCM and C interface, which replaces the IOM-2 interface. The SICOFI-4-C is a fully integrated PCM CODEC and FILTER fabricated in low power 1 CMOS technology for applications in digital communication systems. Based on an advanced digital filter concept, the PEB 2466-H provides excellent transmission performance and high flexibility. The new filter concept (second generation) leads to a maximum of independence between the different filter blocks. Each filter block can be seen like a one to one representative of the corresponding network element. To complete the functionality of the PEB 2466 only two external capacitors per channel are needed. The internal level accuracy is based on a very accurate bandgap reference. The frequency behaviour is mainly determined by digital filters, which do not have any fluctuations. As a result of the new ADC - and DAC - concepts linearity is only limited by second order parasitic effects. Although the device works with only one single 5 V supply there is a very good dynamic range available.
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Four Channel Codec Filter with PCM- and -Controller Interface SICOFI(R)4-C
Version 1.2 1.1 Features
PEB 2466
CMOS
* Single chip programmable CODEC and FILTER to handle four - Central Office - or PABX-channels * Specification according to relevant CCITT, EIA and LSSGR recommendations * Digital signal processing technique P-MQFP-64 * Serial -Controller interface * 2 programmable PCM-interfaces (up to 8 Mbit/s) * Programmable interface to electronic SLICs and transformer solutions for signaling information * High analog driving capability (300 ) for direct driving of transformers * Programmable digital filters to adapt the transmission behaviour especially for - AC impedance matching - transhybrid balancing - frequency response - gain - A/-law conversion * Single 5 V power supply * Advanced low power 0.9 m analog CMOS technology * Low power consumption (< 35 mW per channel) * High performance A/D conversion * High performance D/A conversion * Advanced test capabilities - five digital loops - four analog loops - two programmable tone generators (DTMF possible) - built in self-test - level metering function for system tests * Standard P-MQFP-64 package * Comprehensive development platform available - software for automatic filter coefficient calculation - QSICOS - Hardware development board - STSI 2466 Type PEB 2466-H V1.2
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Ordering Code on request
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Package P-MQFP-64
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General Description 1.2 Pin Configuration (top view) P-MQFP-64
Figure 1
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General Description 1.3 Pin Definition and Functions Input (I) Output (O) Function
Pin No. Symbol
Common Pins for all Channels 24 21
VDDD
GNDD
I I
+ 5 V supply for the digital circuitry 1) Ground Digital, not internally connected to GNDA1,2,3,4 All digital signals are referred to this pin + 5 V Analog supply voltage for channel 1 and 2 1) + 5 V Analog supply voltage for channel 3 and 4
1)
52 61 56
VDDA12 VDDA34 VREF
I I I/O
Reference voltage, has to be connected to a 220 nF cap. to ground, can also be used as virtual ground for analog inputs and outputs (high-ohmic buffer needed !!!) + 5 V Analog supply voltage (100 nF cap. required) Frame synchronization clock, 8 kHz, identifies the beginning of the frame, individual time slots are referenced to this pin, FSC must be synchronous to PCLK Data clock 128 to 8192 kHz, determines the rate at which PCM data is shifted into or out of the PCM-ports PCM-interface: Receive PCM data from PCM-highway B, data for each channel is received in 8 bit bursts every 125 s PCM-interface: Transmit PCM data to PCM-highway B, data for each channel is transmitted in 8 bit burst every 125 s PCM-interface: Transmit control output B, is active if data is transmitted via DXB, active low, open drain PCM-interface: Receive PCM data from PCM-highway A, data for each channel is received in 8 bit bursts every 125 s PCM-interface: Transmit PCM data to PCM-highway A, data for each channel is transmitted in 8 bit burst every 125 s
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57 31
VDDREF
FSC
I I
32
PCLK
I
30
DRB
I
29
DXB
O
28 27
TCB DRA
O I
26
DXA
O
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PEB 2466
General Description 1.3 Pin Definition and Functions (cont'd) Input (I) Output (O) O I I Function PCM-interface: Transmit control output A, is active if data is transmitted via DXA, active low, open drain Reset input - forces the device to default mode, active low Master clock input, 1536, 2048, 4096 or 8192 kHz, synchronous to FSC, must be available if the SICOFI-4-C is used -Controller interface: chip select enable to read or write data, active low -Controller interface: data clock, shifts data from or to device, the maximum clock rate is 8192 kHz -Controller interface: control data input pin, DCLK determines the data rate -Controller interface: control data output pin, DCLK determines the data rate, DOUT is high `Z' if no data is transmitted from the SICOFI-4-C Chopper Clock output, provides a programmable (2 ... 28 ms) output signal (synchronous to MCLK) Chopper Clock output, provides a 256, or 512 or 16384 kHz signal, is synchronous to MCLK Interrupt output pin for channel 1 and 2, active high Interrupt output pin for channel 3 and 4, active high
Pin No. Symbol 25 23 22 TCA RESET MCLK
17 18 19 20
CS DCLK DIN DOUT
I I I O
33 16 34 15
CHCLK1 CHCLK2 INT12 INT34
O O O O
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General Description 1.3 Pin Definition and Functions (cont'd) Input (I) Output (O) Function
Pin No. Symbol
Specific Pins for Channel 1 50 49 51 36 35 41 40 39 38 37 GNDA1 I I O I I O O I/O I/O I/O Ground Analog for channel 1, not internally connected to GNDD or GNDA2,3,4 Analog voice (voltage) input for channel 1, has to be connected to the SLIC by a 39 nF cap. Analog voice (voltage) output for channel 1, has to be connected to the SLIC via a cap. 2) Signaling input pin 0 for channel 1 Signaling input pin 1 for channel 1 Signaling output pin 0 for channel 1 Signaling output pin 1 for channel 1 Bi-directional signaling pin 0 for channel 1 Bi-directional signaling pin 1 for channel 1 Bi-directional signaling pin 2 for channel 1
VIN1 VOUT1
SI1_0 SI1_1 SO1_0 SO1_1 SB1_0 SB1_1 SB1_2
Specific Pins for Channel 2 54 55 53 47 48 42 43 44 45 46 GNDA2 I I O I I O O I/O I/O I/O Ground Analog for channel 2, not internally connected to GNDD or GNDA 1,3,4 Analog voice (voltage) input for channel 2, has to be connected to the SLIC by a 39 nF cap. Analog voice (voltage) output for channel 2, has to be connected to the SLIC via a cap. 2) Signaling input pin 0 for channel 2 Signaling input pin 1 for channel 2 Signaling output pin 0 for channel 2 Signaling output pin 1 for channel 2 Bi-directional signaling pin 0 for channel 2 Bi-directional signaling pin 1 for channel 2 Bi-directional signaling pin 2 for channel 2
VIN2 VOUT2
SI2_0 SI2_1 SO2_0 SO2_1 SB2_0 SB2_1 SB2_2
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General Description 1.3 Pin Definition and Functions (cont'd) Input (I) Output (O) Function
Pin No. Symbol
Specific Pins for Channel 3 59 58 60 2 1 7 6 5 4 3 GNDA3 I I O I I O O I/O I/O I/O Ground Analog for channel 3, not internally connected to GNDD or GNDA1,2,4 Analog voice (voltage) input for channel 3, has to be connected to the SLIC by a 39 nF cap. Analog voice (voltage) output for channel 3, has to be connected to the SLIC via a cap. 2) Signaling input pin 0 for channel 3 Signaling input pin 1 for channel 3 Signaling output pin 0 for channel 3 Signaling output pin 1 for channel 3 Bi-directional signaling pin 0 for channel 3 Bi-directional signaling pin 1 for channel 3 Bi-directional signaling pin 2 for channel 3
VIN3 VOUT3
SI3_0 SI3_1 SO3_0 SO3_1 SB3_0 SB3_1 SB3_2
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General Description 1.3 Pin Definition and Functions (cont'd) Input (I) Output (O) Function
Pin No. Symbol
Specific Pins for Channel 4 63 64 62 13 14 8 9 10 11 12
1) 2)
GNDA4
I I O I I O O I/O I/O I/O
Ground Analog for channel 4, not internally connected to GNDD or GNDA1,2,3 Analog voice (voltage) input for channel 4, has to be connected to the SLIC by a 39 nF cap. Analog voice (voltage) output for channel 4, has to be connected to the SLIC via a cap. 2) Signaling input pin 0 for channel 4 Signaling input pin 1 for channel 4 Signaling output pin 0 for channel 4 Signaling output pin 1 for channel 4 Bi-directional signaling pin 0 for channel 4 Bi-directional signaling pin 1 for channel 4 Bi-directional signaling pin 2 for channel 4
VIN4 VOUT4
SI4_0 SI4_1 SO4_0 SO4_1 SB4_0 SB4_1 SB4_2
A 100 nF cap. should be used for blocking these pins, see also on page 82 The value for the capacitor needed, depends on the input impedance of the `SLIC'-circuitry. For choosing the appropriate values see figure on page 71.
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Functional Description 2 2.1 Functional Description SICOFI(R)-4-C Principles
The change from 2 m to 1 m CMOS process requires new concepts in the realization of the analog functions. High performance (in the terms of gain, speed, stability ...) 1 m CMOS devices cannot withstand more than 5.5 V of supply-voltage. On that account the negative supply voltage VSS of the previous SICOFIs is omitted. This is a benefit for the user but it makes a very high demand on the analog circuitry. ADC and DAC are changed to Sigma-Delta-concepts to fulfill the stringent requirements on the dynamic parameters. Using 1 m CMOS does not only lead to problems - it is the only acceptable solution in terms of area and power consumption for the integration of more than two SICOFI channels on a single chip. It is rather pointless to implement 4 codec-filter-channels on one chip with pure analog circuitry. The use of a DSP-concept (the SICOFI and the SICOFI-2-approach) for this function is a must for an adequate four channel architecture.
Figure 2 SICOFI(R)-4 C Signal Flow Graph (for any channel)
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PEB 2466
Functional Description Transmit Path The analog input signal has to be DC-free connected by an external capacitor because there is an internal virtual reference ground potential. After passing a simple antialiasing prefilter (PREFI) the voice signal is converted to a 1-bit digital data stream in the Sigma-Delta-converter. The first downsampling steps are done in fast running digital hardware filters. The following steps are implemented in the micro-code which has to be executed by the central Digital Signal Processor. This DSP-machine is able to handle the workload for all four channels. At the end the fully processed signal (flexibly programmed in many parameters) is transferred to the PCM- interface in a PCM-compressed signal representation. Receive Path The digital input signal is received via the PCM interface. Expansion, PCM-Law-pass-filtering, gain correction and frequency response correction are the next steps which are done by the DSP-machine. The upsampling interpolation steps are again processed by fast hardware structures to reduce the DSP-workload. The upsampled 1-bit data stream is then converted to an analog equivalent which is smoothed by a POST-Filter (POFI). As the signal VOUT is also referenced to an internal virtual ground potential, an external capacitor is required for DC-decoupling. Loops There are two loops implemented. The first is to generate the AC-input impedance (IM) and the second is to perform a proper hybrid balancing (TH). A simple extra path IM2 (from the transmit to the receive path) supports the impedance matching function. Test Features There are four analog and five digital test loops implemented in the SICOFI-4. For special tests it is possible to Cut Off the receive and the transmit path at two different points.
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Functional Description
Voice Data
PCM Interface
HW-Filter
HW-Filter
Analog OUT Analog IN
D A A D D A A D
D A A D D A A D
Analog OUT Analog IN
DSP
HW-Filter
HW-Filter
Analog OUT Analog IN
Analog OUT Analog IN
Command Indication Command Indication
Signaling
C Interface
Signaling
Command Indication Command Indication
ITB07256
Signaling Control Data
Signaling
Figure 3 SICOFI(R)-4-C Block Diagram The SICOFI-4-C bridges the gap between analog and digital voice signal transmission in modern telecommunication systems. High performance oversampling Analog-to-Digital Converters (ADC) and Digital-to-Analog Converters (DAC) provide the conversion accuracy required. Analog antialiasing prefilters (PREFI) and smoothing postfilters (POFI) are included. The connection between the ADC and the DAC (with high sampling rate) and the DSP, is done by specific Hardware Filters, for filtering like interpolation and decimation. The dedicated Digital Signal Processor (DSP) handles all the algorithms necessary e.g. for PCM bandpass filtering, sample rate conversion and PCM companding. The PCM-interface handles digital voice transmission, a serial C-interface handles SICOFI-4-C feature control and transparent access to the SICOFI-4-C command and indication pins. To program the filters, precalculated sets of coefficients are downloaded from the system to the on-chip Coefficient-RAM (CRAM).
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Functional Description 2.2 The PCM-interface
Two serial PCM-interfaces are used for the transfer of A- or -law compressed voice data. The PCM-interface consist of 8 pins: PCLK: FSC: DRA: DRB: DXA: DXB: TCA: TCB: PCM-Clock, 128 kHz to 8192 kHz Frame Synchronization Clock, 8 kHz Receive Data input for PCM-highway A Receive Data input for PCM-highway B Transmit Data output for PCM-highway A Transmit Data output for PCM-highway B Transmit Control Output for PCM-highway A, active low during transmission Transmit Control Output for PCM-highway B, active low during transmission
The Frame Sync FSC pulse identifies the beginning of a receive and transmit frame for all of the four channels. The PCLK clock is the signal to synchronize the data transfer on both lines DXA (DXB) and DRA (DRB). Bytes in all channels are serialized to 8 bit width and MSB first. As a default setting, the rising edge indicates the start of the bit, while the falling edge is used to latch the contents of the received data on DRA (DRB). If the double clock rate is chosen (twice the transmission rate) the first rising edge indicates the start of a bit, while the second falling edge is used for latching the contents of the data line DRA (DRB) by default. The data rate of the interface can vary from 2 x 128 kbit/s to 2 x 8192 kbit/s (2 highways) A frame may consist of up to 128 time slots of 8 bits each. In the Time Slot Configuration Registers CR5 and CR6 the user can select an individual time slot, and an individual PCM-highway, for any of the four voice channels. Receive and transmit time slots can also be programmed individually. An extra delay of up to 7 clocks, valid for all channels, as well as the sampling slope may be programmed (see XR6). When the SICOFI-4-C is transmitting data on DXA (DXB), pin TCA (TCB) is activated to control an extra external driving device.
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Functional Description The following table shows possible examples for the PCM-interface, other frequencies like 768 kHz or 1536 kHz are also possible. Table 1 Frequency [kHz] 128 256 256 512 512 1024 1024 2048 2048 4096 4096 8192 8192 Formula Formula f f Single/Double [1/2] 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 Time Slots [per highway] 2 2 4 4 8 8 16 16 32 32 64 64 128 f/64 f/128 Datarate [kbit/s per highway] 128 128 256 256 512 512 1024 1024 2048 2048 4096 4096 8192 f f/2
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Functional Description
Figure 4 Example for Single Clock Rate, 128 kbit/s
Figure 5 Example for Double Clock Rate, 128 kbit/s
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Functional Description
125 s FSC
PCLK Time-Slot DRA High 'Z' High 'Z' 0123 Time-Slot 31
DXA
TCA Detail A
ITD07259
Figure 6 Example for 2048 kbit/s, Single Clock Operation, only Highway A used
FSC Clock PCLK 0 1 2 3 4 5 6 7
DRA Bit DXA High 'Z' 7 6 5
Voice Data 4 3 2 1 0 High 'Z'
Voice Data
TCA
ITD07260
Figure 7 Detail A For special purposes the DRA/B and DXA/B pins may be strapped together, and form bi-directional data-`pin' (like SIP with the SLD-bus).
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Functional Description 2.3 The -Controller Interface
The internal configuration registers, the signaling interface, and the Coefficient-RAM (CRAM) of the SICOFI-4-C are programmable via a serial -Controller interface. The -Controller interface consists of four lines: CS, DCLK, DIN and DOUT: CS is used to start a serial access to the SICOFI-4-C registers and Coefficient-RAM. Following a falling edge of CS, the first eight bits received on DIN specify the command. Subsequent data bytes (number depends on command) are stored in the selected configuration registers or the selected part of the Coefficient-RAM.
CS
DCLK
DIN
765432107654321076543210 Control Data Byte 1 High 'Z'
ITD07261
Data Byte 2
DOUT
Figure 8 Example for a Write Access, with Two Data Bytes Transferred If the first eight bits received via DIN specify a read-command, the SICOFI-4 will start a response via DOUT with its specific address byte (81H). After transmitting this identification, the specified n data bytes (contents of configuration registers, or contents of the CRAM) will follow on DOUT.
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Functional Description
CS
DCLK
DIN
76543210 Control
DOUT
High 'Z'
7654321076543210 Identification Data Byte 1
High 'Z'
ITD07262
Figure 9 Example for a Read Access, with One Data Byte Transferred via DOUT The data transfer is synchronized by the DCLK input. The contents of DIN is latched at the rising edge of DCLK, while DOUT changes with the falling edge of DCLK. During execution of commands that are followed by output data (read commands), the device will not accept any new command via DIN. The data transfer sequence can be broken by setting CS to high. To reduce the number of connections to the P DIN and DOUT may be strapped together, and form a bi-directional data-`pin'. For special applications a byte by byte transfer is needed. This can be done by prolonging the high time of DCLK for a user defined `waiting time' after transferring any byte.
CS
DCLK High 'Z'
DATA
76543210 Control-Byte
7654321 Identification
0
76543210 Data Byte 1
ITD09570
Figure 10 Example for a Write/Read Access, with a Byte by Byte Transfer, and DIN and DOUT Strapped Together The Identification Byte is "81H" for the PEB 2466.
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Programming the SICOFI(R)-4-C 3 Programming the SICOFI(R)-4-C
With the appropriate commands, the SICOFI-4-C can be programmed and verified very flexibly via the -Controller interface. With the first byte received via DIN, one of 3 different types of commands (SOP, XOP and COP) is selected. Each of those can be used as a write or read command. Due to the extended SICOFI-4-C feature control facilities, SOP, COP and XOP commands contain additional information (e.g. number of subsequent bytes) for programming (write) and verifying (read) the SICOFI-4-C status. A write command is followed by up to 8 bytes of data. The SICOFI-4-C responds to a read command with its specific identification and the requested information, that is up to 8 bytes of data. 3.1 Types of Command and Data Bytes
The 8-bit bytes have to be interpreted as either commands or status information stored in Configuration Registers or the Coefficient-RAM. There are three different types of SICOFI -4-C commands which are selected by bit 3 and 4 as shown below. SOP Bit 7 AD2 XOP Bit 7 0 COP Bit 7 AD2 AD1 0 1 1 filter coefficient setting/monitoring 0 AD1 1 0 C/I1) channel configuration/evaluation 0 STATUS OPERATION: SICOFI-4-C status setting/monitoring 0
EXTENDED OPERATION:
COEFFICIENT OPERATION:
Note:
1)
Command/Indication (signaling) channel.
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Programming the SICOFI(R)-4-C Storage of Programming Information 6 configuration registers per channel: 8 common configuration registers: 1 Coefficient-RAM per channel: 3.2 CR0, CR1, CR2, CR3, CR4 and CR5 accessed by SOP commands XR0 .. XR7 accessed by XOP commands, valid for all 4 channels CRAM accessed by COP commands
Examples for SICOFI(R)-4 Commands
SOP - Write Commands DIN SOP-Write 1 Byte CR0 DIN SOP-Write 2 Bytes CR1 CR0 DIN SOP-Write 3 Bytes CR2 CR1 CR0 DIN SOP-Write 4 Bytes CR3 CR2 CR1 CR0 76543210 010000 Data 76543210 010001 Data Data 76543210 010010 Data Data Data 76543210 010011 Data Data Data Data Bit Bit Bit Bit 76543210 Idle Idle 76543210 Idle Idle Idle 76543210 Idle Idle Idle Idle 76543210 Idle Idle Idle Idle Idle DOUT DOUT DOUT DOUT
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Programming the SICOFI(R)-4-C XOP - Write Commands DIN XOP-Write 2 Bytes XR1 XR0 DIN XOP-Write 3 Bytes XR2 XR1 XR0 COP - Write Commands DIN COP-Write 4 Bytes Coeff. 3 Coeff. 2 Coeff. 1 Coeff. 0 DIN COP-Write 8 Bytes Coeff. 7 Coeff. 6 Coeff. 5 Coeff. 4 Coeff. 3 Coeff. 2 Coeff. 1 Coeff. 0 76543210 00 Data Data Data Data 76543210 00 Data Data Data Data Data Data Data Data Bit Bit 76543210 Idle Idle Idle Idle Idle 76543210 Idle Idle Idle Idle Idle Idle Idle Idle Idle DOUT DOUT 76543210 011001 Data Data 76543210 011010 Data Data Data Bit Bit 76543210 Idle Idle Idle 76543210 Idle Idle Idle Idle DOUT DOUT
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Programming the SICOFI(R)-4-C SOP - Read Commands DIN SOP-Read 1 Byte 76543210 110000 Idle Idle DIN SOP-Read 2 Bytes 76543210 110001 Idle Idle Idle DIN SOP-Read 3 Bytes 76543210 110010 Idle Idle Idle Idle DIN SOP-Read 4 Bytes 76543210 110011 Idle Idle Idle Idle Idle Bit Bit Bit Bit 76543210 Idle 1 0 0 0 0 0 0 1 Identification Data 76543210 Idle 1 0 0 0 0 0 0 1 Identification Data Data 76543210 Idle 1 0 0 0 0 0 0 1 Identification Data Data Data 76543210 Idle 1 0 0 0 0 0 0 1 Identification Data Data Data Data CR3 CR2 CR1 CR0 CR2 CR1 CR0 DOUT CR1 CR0 DOUT CR0 DOUT DOUT
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Programming the SICOFI(R)-4-C XOP-Read Commands DIN XOP-Read 1 Byte 76543210 111000 Idle Idle DIN XOP-Read 2 Bytes 76543210 111001 Idle Idle Idle DIN XOP-Read 3 Bytes 76543210 111010 Idle Idle Idle Idle Bit Bit Bit 76543210 Idle 1 0 0 0 0 0 0 1 Identification Data 76543210 Idle 1 0 0 0 0 0 0 1 Identification Data Data 76543210 Idle 1 0 0 0 0 0 0 1 Identification Data Data Data XR2 XR1 XR0 XR1 XR0 DOUT XR0 DOUT DOUT
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Programming the SICOFI(R)-4-C COP-Read Commands DIN COP-Read 4 Bytes 76543210 101 Idle Idle Idle Idle Idle DIN COP-Read 8 Bytes 76543210 100 Idle Idle Idle Idle Idle Idle Idle Idle Idle Bit Bit 76543210 Idle 1 0 0 0 0 0 0 1 Identification Data Data Data Data 76543210 Idle 1 0 0 0 0 0 0 1 Identification Data Data Data Data Data Data Data Data Coeff. 8 Coeff. 7 Coeff. 6 Coeff. 5 Coeff. 4 Coeff. 3 Coeff. 2 Coeff. 1 Coeff. 3 Coeff. 2 Coeff. 1 Coeff. 0 DOUT DOUT
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Programming the SICOFI(R)-4-C Example of a Mixed Command DIN SOP-Write 4 Bytes CR3 CR2 CR1 CR0 XOP-Write 2 Bytes XR1 XR0 COP-Write 4 Bytes Coeff. 3 Coeff. 2 Coeff. 1 Coeff. 0 SOP-Read 3 Bytes 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 010011 Data Data Data Data 011001 Data Data 001 Data Data Data Data 110010 Idle Idle Idle Idle COP-Read 4 Bytes 101 Idle Idle Idle Idle Idle XOP-Read 1 Byte 111000 Idle Idle Idle Idle Idle Idle Idle Idle Idle Idle Idle Idle Idle Idle Idle Idle 1 0 0 0 0 0 0 1 Identification Data Data Data Idle 1 0 0 0 0 0 0 1 Identification Data Data Data Data Idle 1 0 0 0 0 0 0 1 Identification Data XR0 Coeff. 3 Coeff. 2 Coeff. 1 Coeff. 0 CR2 CR1 CR0 DOUT
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Programming the SICOFI(R)-4-C 3.3 SOP Command
To modify or evaluate the SICOFI-4-C status, the contents of up to 6 configuration registers CR0 .. CR7 may be transferred to or from the SICOFI-4-C. This is started by a SOP-Command (status operation command). Bit 7 AD2 AD AD1 RW 1 0 LSEL2 LSEL1 0 LSEL0
Address Information AD = 00 AD = 01 AD = 10 AD = 11 SICOFI-4-C - channel 1 is addressed with this command SICOFI-4-C - channel 2 is addressed with this command SICOFI-4-C - channel 3 is addressed with this command SICOFI-4-C - channel 4 is addressed with this command
RW
Read/Write Information: Enables reading from the SICOFI-4-C or writing information to the SICOFI-4-C RW = 0 RW = 1 Write to SICOFI-4 C Read from SICOFI-4 C
LSEL
Length select information (see also programming procedure) This field identifies the number of subsequent data bytes LSEL = 000 LSEL = 001 LSEL = 010 LSEL = 011 LSEL = 100 LSEL = 101 1 byte of data is following (CR0) 2 bytes of data are following (CR1, CR2) 3 bytes of data are following (CR2, CR1, CR0) 4 bytes of data are following (CR3, CR2, CR1, CR0) 5 bytes of data are following (CR4, CR3, CR2, CR1, CR0) 6 bytes of data are following (CR5, CR4, CR3, CR2, CR1, CR0)
All other codes are reserved for future use !
Note: If only one configuration register requires modification, for example CR5, this can be accomplished by setting LSEL = 101 and releasing pin CS after CR5 is written.
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Programming the SICOFI(R)-4-C 3.3.1 CR0 Configuration Register 0
Configuration register CR0 defines the basic SICOFI-4-C settings, which are: enabling/ disabling the programmable digital filters. Bit 7 TH TH IM/R1 FRX FRR AX AR 0 TH-SEL
Enable TH- (Trans Hybrid Balancing) Filter TH = 0: TH = 1: TH-filter disabled TH-filter enabled
IM/R1
Enable IM-(Impedance Matching) Filter and R1-Filter IM/R1 = 0: IM/R1 = 1: IM-filter and R1-filter disabled IM-filter and R1-filter enabled
FRX
Enable FRX (Frequency Response Transmit)-Filter FRX = 0: FRX = 1: FRX-filter disabled FRX-filter enabled
FRR
Enable FRR (Frequency Response Receive)-Filter FRR = 0: FRR = 1: FRR-filter disabled FRR-filter enabled
AX
Enable AX-(Amplification/Attenuation Transmit) Filter AX = 0: AX = 1: AX-filter disabled AX-filter enabled
AR
Enable AR-(Amplification/Attenuation Receive) Filter AR = 0: AR = 1: AX-filter disabled AX-filter enabled
TH-SEL
2 bit field to select one of four programmed TH-filter coefficient sets TH-Sel = 0 0: TH-filter coefficient set 1 is selected TH-Sel = 0 1: TH-filter coefficient set 2 is selected TH-Sel = 1 0: TH-filter coefficient set 3 is selected TH-Sel = 1 1: TH-filter coefficient set 4 is selected
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Programming the SICOFI(R)-4-C 3.3.2 CR1 Configuration Register 1
Configuration register CR1 selects tone generator modes and other operation modes. Bit 7 ETG2 ETG2 ETG1 PTG2 PTG1 LAW 0 0 0 PU
Enable programmable tone generator 2 1) ETG2 = 0: ETG2 = 1: Programmable tone generator 2 is disabled Programmable tone generator 2 is enabled
ETG1
Enable programmable tone generator 1 ETG1 = 0: ETG1 = 1: Programmable tone generator 1 is disabled Programmable tone generator 1 is enabled
PTG2
User programmed frequency or fixed frequency is selected PTG2 = 0: PTG2 = 1: Fixed frequency for tone generator 2 is selected (1 kHz) Programmed frequency for tone generator 2 is selected
PTG1
User programmed frequency or fixed frequency is selected PTG1 = 0: PTG1 = 1: Fixed frequency for tone generator 1 is selected (1 kHz) Programmed frequency for tone generator 1 is selected
LAW
PCM - law selection LAW = 0: LAW = 1: A-Law is selected -Law (255 PCM) is selected
PU
Power UP, sets the addressed channel to Power Up / Down PU = 0: PU = 1: The addressed channel is set to Power Down (standby) The addressed channel is set to Power Up (operating)
1)
Tone generator 2 is not available if Level Metering Function is enabled!
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Programming the SICOFI(R)-4-C 3.3.3 Bit 7 COT/R COT/R 0 IDR LM LMR CR2 Configuration Register 2 0 V+T
Selection of Cut off Transmit/Receive Paths 0 0 0: 0 0 1: 0 1 0: Normal Operation COT16 COT8 Cut Off Transmit Path at 16 kHz (input of TH-Filter) Cut Off Transmit Path at 8 kHz (input of compression, output is zero for -law, 1 LSB for A-law) Cut Off Receive Path at 4 MHz (POFI-output) Cut Off Receive Path at 64 kHz (IM-filter input)
1 0 1: 1 1 0: IDR
COR4M COR64
Initialize Data RAM IDR = 0: IDR = 1: Normal operation is selected Contents of Data RAM is set to 0 (used for production test purposes)
LM
Level Metering function 1) LM = 0: LM = 1: Level metering function is disabled Level metering function is enabled
LMR
Result of Level Metering function (this bit can not be written) LMR = 0: Level detected was lower than the reference LMR = 1: Level detected was higher than the reference
V+T
Add Voice signal and Tone Generator signal V+T = 0: V+T = 1: Voice or Tone Generator is fed to the DAC Voice and Tone Generator Signals are added, and fed to the Digital to Analog Converter
1)
Explanation of the level metering function: A signal fed to A/-Law compression via AX- and HPX-filters (from a digital loop, or externally via VIN), is rectified, and the power is measured. If the power exceeds a certain value, loaded to XR7, bit LMR is set to `1'. The power of the incoming signal can be adjusted by AX-filters.
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Transmit Path PCMOUT CMP DS1 DS2 DS3 AX2* FRX* AX1* HPX COT-16K COT-PCM
ALB-8K DLB-PCM ALB-PCM DLB-64K DLB-128K
Figure 11 `CUT OFF's' and Loops
IM 1* TH* TG1, 2 + US3 US2 R1* US1 AR2* FRR* AR1* HPR EXP PCMIN COR-64K 256 kHz 128 kHz 64 kHz Receive Path 16 kHz 8 kHz
ITS09608
VIN
AGX
A
D
DLB-4M
ALB-4M
ALB-PFI
DLB-ANA
IM2*
35
VOUT
AGR
D
A
COR-PFI
4 MHz
PEB 2466
Programming the SICOFI(R)-4-C
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Programming the SICOFI(R)-4-C 3.3.4 Bit 7 Test-Loops AGX AGR D-HPX CR3 Configuration Register 3 0 D-HPR
Test-Loops 4 bit field for selection of Analog and Digital Loop Backs 0 0 0 0: 0 0 0 1: 0 0 1 1: 0 1 0 0: 0 1 0 1: 1 0 0 0: 1 0 0 1: 1 1 0 0: 1 1 0 1: 1 1 1 1: AGX ALB-PFI ALB-4M ALB-PCM ALB-8K DLB-ANA DLB-4M DLB-128K DLB-64K DLB-PCM No loop back is selected (normal operation) Analog loop back via PREFI-POFI is selected Analog loop back via 4 MHz is selected Analog loop back via 8 kHz (PCM) is selected (attention: special settings necessary) Analog loop back via 8 kHz (linear) is selected Digital loop back via analog port is selected Digital loop back via 4 MHz is selected Digital loop back via 128 kHz is selected Digital loop back via 64 kHz is selected Digital loop back via PCM-registers is selected
Analog gain in transmit direction AGX = 0: AGX = 1: Analog gain is disabled Analog gain is enabled (6.02 dB amplification)
AGR
Analog gain in receive direction AGR = 0: AGR = 1: Analog gain is disabled Analog gain is enabled (6.02 dB attenuation)
D-HPX
Disable highpass in transmit direction D-HPX = 0: D-HPX = 1: Transmit high pass is enabled Transmit high pass is disabled1)
D-HPR
Disable highpass in receive direction D-HPR = 0: Receive high pass is enabled D-HPR = 1: Receive high pass is disabled2)
1) 2)
In this case the transmit-path signal is attenuated 0.06 dB In this case the receive-path signal is attenuated 0.12 dB
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Programming the SICOFI(R)-4-C 3.3.5 CR4 Configuration Register 4
Configuration register CR4, sets the receiving time slot and the receiving PCM-highway. Bit 7 R-WAY R-WAY RS6 RS5 RS4 RS3 RS2 RS1 0 RS0
Selects the PCM-Highway for the receiving of PCM-data R-WAY = 0: R-WAY = 1: PCM-Highway A is selected PCM-Highway B is selected
RS[6:0]
Selects the time slot (0 to 127) used for receiving the PCM-data The time slot-number is binary coded. 0 0 0 0 0 0 0: 0 0 0 0 0 0 1: .... 1 1 1 1 1 1 0: 1 1 1 1 1 1 1: Time slot 126 is selected Time slot 127 is selected Time slot 0 is selected Time slot 1 is selected
3.3.6
CR5 Configuration Register 5
Configuration register CR5, sets the transmit time slot and the transmit PCM-highway. Bit 7 X-WAY X-WAY XS6 XS5 XS4 XS3 XS2 XS1 0 XS0
Selects the PCM-Highway for transmitting PCM-data X-WAY = 0: X-WAY = 1: PCM-Highway A is selected PCM-Highway B is selected
XS[6:0]
Selects the time slot (0 to 127) used for transmitting the PCM-data The time slot-number is binary coded. 0 0 0 0 0 0 0: 0 0 0 0 0 0 1: .... 1 1 1 1 1 1 0: 1 1 1 1 1 1 1: Time slot 126 is selected Time slot 127 is selected
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Time slot 0 is selected Time slot 1 is selected
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Programming the SICOFI(R)-4-C 3.4 COP Command
With a COP command coefficients for the programmable filters can be written to the SICOFI-4-C coefficient-RAM or read from the Coefficient-RAM via the -Controller interface for verification Bit 7 AD2 AD AD1 Address AD = 0 0 AD = 0 1 AD = 1 0 AD = 1 1 RW Read/Write RW = 0 RW = 1 CODE Subsequent data is written to the SICOFI-4-C Read data from SICOFI-4-C SICOFI-4-C- channel 1 is addressed SICOFI-4-C- channel 2 is addressed SICOFI-4-C- channel 3 is addressed SICOFI-4-C- channel 4 is addressed RW 0 CODE3 CODE2 CODE1 0 CODE0
Includes number of following bytes and filter-address 0 0 0 0 TH-Filter coefficients (part 1) 0 0 0 1 TH-Filter coefficients (part 2) 0 0 1 0 TH-Filter coefficients (part 3) (followed by 8 bytes of data) (followed by 8 bytes of data) (followed by 8 bytes of data)
0 1 0 0 IM/R1-Filter coefficients (part 1) (followed by 8 bytes of data) 0 1 0 1 IM/R1-Filter coefficients (part 2) (followed by 8 bytes of data) 0 1 1 0 FRX-Filter coefficients 0 1 1 1 FRR-Filter coefficients 1 0 0 0 AX-Filter coefficients 1 0 0 1 AR-Filter coefficients 1 1 0 0 TG 1- coefficients 1 1 0 1 TG 2- coefficients (followed by 8 bytes of data) (followed by 8 bytes of data) (followed by 4 bytes of data) (followed by 4 bytes of data) (followed by 4 bytes of data) (followed by 4 bytes of data)
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Programming the SICOFI(R)-4-C How to Program the Filter Coefficients TH-Filter: Four sets of TH-filter coefficients can be loaded to the SICOFI-4-C. Each of the four sets can be selected for any of the four SICOFI-4-C channels, by setting the value of TH-Sel in configuration register CR2. Coefficient set 1 is loaded to the SICOFI-4-C via channel 1, set 2 is loaded via channel 2 and so on.
AX, AR, IM/R1, FRX, FRR-Filter, Tone-Generators: An individual coefficient set is available for each of the four channels.
Figure 12
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Programming the SICOFI(R)-4-C 3.5 XOP Command
With the XOP command the SICOFI-4-C digital command/indication interface to a SLIC is configured and evaluated. Also other common functions are assigned with this command. Bit 7 RST RST 0 RW 1 1 LSEL2 LSEL1 0 LSEL0
Software Reset (same as RESET-pin, valid for all 4 channels) RST = 1: RST = 0: Reset No operation
RW
Read / Write Information: Enables reading from the SICOFI-4-C or writing information to the SICOFI-4-C RW = 0: RW = 1: Write to SICOFI-4-C Read from SICOFI-4-C
LSEL
Length select information, for setting the number of subsequent data bytes LSEL = 000: 1 byte of data is following (XR0) LSEL = 001: 2 bytes of data are following (XR1, XR0) : LSEL = 111: 8 bytes of data are following (XR7, XR6, XR5, XR4, XR3, XR2, XR1, XR0)
Note: All other codes are reserved for future use! If only one configuration register requires modification, for example XR5, this can be accomplished by setting LSEL =101 and releasing pin CS after XR5 is written.
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Programming the SICOFI(R)-4-C 3.5.1 XR0 Extended Register 0
The signaling connection between SICOFI-4-C and a SLIC is performed by master device the SICOFI-4-C signaling input and output pins and Configuration Register XR0... XR4. Data received from the upstream master device are transferred to signaling output pins (SO, SB). Data at the signaling input pins are transferred to the upstream controller. In Connection with XOP-Read Commands Bit 7 SI4_1 SI4_1 SI4_0 SI3_1 SI3_0 SI2_1 SI2_0 SI1_1 SI1_0 SI4_0 SI3_1 SI3_0 SI2_1 SI2_0 SI1_1 0 SI1_0
Status of pin SI4_1 is transferred to the upstream master device Status of pin SI4_0 is transferred to the upstream master device Status of pin SI3_1 is transferred to the upstream master device Status of pin SI3_0 is transferred to the upstream master device Status of pin SI2_1 is transferred to the upstream master device Status of pin SI2_0 is transferred to the upstream master device Status of pin SI1_1 is transferred to the upstream master device Status of pin SI1_0 is transferred to the upstream master device
In Connection with XOP-Write Commands Bit 7 SO4_1 SO4_1 SO4_0 SO3_1 SO3_0 SO2_1 SO2_0 SO1_1 SO1_0 SO4_0 SO3_1 SO3_0 SO2_1 SO2_0 SO1_1 0 SO1_0
Pin SO4_1 is set to the assigned value Pin SO4_0 is set to the assigned value Pin SO3_1 is set to the assigned value Pin SO3_0 is set to the assigned value Pin SO2_1 is set to the assigned value Pin SO2_0 is set to the assigned value Pin SO1_1 is set to the assigned value Pin SO1_0 is set to the assigned value
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Programming the SICOFI(R)-4-C 3.5.2 XR1 Extended Register 1
This register transfers information to or from the programmable signaling pins. Bit 7 SB4_1 SB4_0 SB3_1 SB3_0 SB2_1 SB2_0 SB1_1 0 SB1_0
In Connection with a XOP-Read Command SB4_1 SB4_0 SB3_1 SB3_0 SB2_1 SB2_0 SB1_1 SB1_0 If input: status of pin SB4_1 is transferred upstream If input: status of pin SB4_0 is transferred upstream If input: status of pin SB3_1 is transferred upstream If input: status of pin SB3_0 is transferred upstream If input: status of pin SB2_1 is transferred upstream If input: status of pin SB2_0 is transferred upstream If input: status of pin SB1_1 is transferred upstream If input: status of pin SB1_0 is transferred upstream
In Connection with a XOP-Write Command SB4_1 SB4_0 SB3_1 SB3_0 SB2_1 SB2_0 SB1_1 SB1_0 If output: pin SB4_1 is set to the assigned value If output: pin SB4_0 is set to the assigned value If output: pin SB3_1 is set to the assigned value If output: pin SB3_0 is set to the assigned value If output: pin SB2_1 is set to the assigned value If output: pin SB2_0 is set to the assigned value If output: pin SB1_1 is set to the assigned value If output: pin SB1_0 is set to the assigned value
Note: After a `Reset' of the device, all programmable pins are input pins!
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PEB 2466
Programming the SICOFI(R)-4-C 3.5.3 XR2 Extended Register 2
This register controls the direction of the programmable signaling pins. Bit 7 0 PSB4_1 PSB4_0 PSB3_1 PSB3_0 PSB2_1 PSB2_0 PSB1_1 PSB1_0 PSB4_1 PSB4_1 = 0: PSB4_1 = 1: PSB4_0 PSB4_0 = 0: PSB4_0 = 1: PSB3_1 PSB3_1 = 0: PSB3_1 = 1: PSB3_0 PSB3_0 = 0: PSB3_0 = 1: PSB2_1 PSB2_1 = 0: PSB2_1 = 1: PSB2_0 PSB2_0 = 0: PSB2_0 = 1: PSB1_1 PSB1_1 = 0: PSB1_1 = 1: PSB1_0 PSB1_0 = 0: PSB1_0 = 1: Programmable bi-directional signaling pin SB4_1 is programmed Pin SB4_1 is indication input Pin SB4_1 is command output Programmable bi-directional signaling pin SB4_0 is programmed pin SB4_0 is indication input Pin SB4_0 is command output Programmable bi-directional signaling pin SB3_1 is programmed Pin SB3_1 is indication input Pin SB3_1 is command output Programmable bi-directional signaling pin SB3_0 is programmed Pin SB3_0 is indication input Pin SB3_0 is command output Programmable bi-directional signaling pin SB2_1 is programmed Pin SB2_1 is indication input Pin SB2_1 is command output Programmable bi-directional signaling pin SB2_0 is programmed Pin SB2_0 is indication input Pin SB2_0 is command output Programmable bi-directional signaling pin SB1_1 is programmed Pin SB1_1 is indication input Pin SB1_1 is command output Programmable bi-directional signaling pin SB1_0 is programmed Pin SB1_0 is indication input Pin SB1_0 is command output
Note: After a `Reset' of the device, all programmable pins are input pins!
Semiconductor Group 43 02.97
PEB 2466
Programming the SICOFI(R)-4-C 3.5.4 XR3 Extended Register 3
This register transfers information to or from the programmable signaling pins and configures these pins. Bit 7 SB4_2 SB3_2 SB2_2 SB1_2 0 PSB4_2 PSB3_2 PSB2_2 PSB1_2
In Connection with a XOP-Read Command SB4_2 SB3_2 SB2_2 SB1_2 If input: status of pin SB4_2 is transferred upstream If input: status of pin SB3_2 is transferred upstream If input: status of pin SB2_2 is transferred upstream If input: status of pin SB1_2 is transferred upstream
In Connection with a XOP-Write Command SB4_2 SB3_2 SB2_2 SB1_2 PSB4_2 PSB4_2 = 0: PSB4_2 = 1: PSB3_2 PSB3_2 = 0: PSB3_2 = 1: PSB2_2 PSB2_2 = 0: PSB2_2 = 1: PSB1_2 PSB1_2 = 0: PSB1_2 = 1: If output: pin SB4_2 is set to the assigned value If output: pin SB3_2 is set to the assigned value If output: pin SB2_2 is set to the assigned value If output: pin SB1_2 is set to the assigned value Programmable bi-directional signaling pin SB4_2 is programmed Pin SB4_2 is indication input Pin SB4_2 is command output Programmable bi-directional signaling pin SB3_2 is programmed Pin SB3_2 is indication input Pin SB3_2 is command output Programmable bi-directional signaling pin SB2_2 is programmed Pin SB2_2 is indication input Pin SB2_2 is command output Programmable bi-directional signaling pin SB1_2 is programmed Pin SB1_2 is indication input Pin SB1_2 is command output
Note: After a `Reset' of the device, all programmable pins are input pins!
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PEB 2466
Programming the SICOFI(R)-4-C 3.5.5 XR4 Extended Register 4
Register XR4 provides two optional functions: debouncing of signaling input changes, and the configuration of the programmable output pin CHCLK1. Bit 7 N Signaling Debounce Interval N To restrict the rate of changes on signaling input pins transferred, deglitching of the status information from the SLIC may be applied. New status information will be read into registers XR0, XR1, XR2 and XR3, and an interrupt on pin INT12 (INT34) will be generated, after it has been stable for N milliseconds. N is programmable in the range of 2 to 30 ms in steps of 2 ms, with N = 0 the debouncing is disabled. Field N 0 0 0 . . 1 1 0 0 0 . . 1 1 0 0 1 . . 1 1 0 1 0 . . 0 1 Debounce Interval Time Debounce and interrupt generation is disabled Debounce period 2 ms Debounce period 4 ms . . Debounce period 28 ms Debounce period 30 ms T 0
Configuration of CHCLK1 Field T 0 0 0 . . 1 1 0 0 0 . . 1 1 0 0 1 . . 1 1 0 1 0 . . 0 1 Frequency applied to Pin CHCLK1 CHCLK1 is set to 1 permanently T is 2ms T is 4ms . . T is 28 ms CHCLK1 is set to 0 permanently
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45
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PEB 2466
Programming the SICOFI(R)-4-C 3.5.6 XR5 Extended Register 5
This register contains additional configuration items valid for all 4 channels Bit 7 MCLK-SEL MCLK-SEL CRSH_A CRSH_B CHCLK2 0 Version
Selects Master Clock frequency, that has to be applied to pin MCLK The MCLK signal has to synchronous to the 8 kHz FSC-signal. 0 0: 0 1: 1 0: 1 1: 1536 kHz selected 2048 kHz selected 4096 kHz selected 8192 kHz selected
CRSH_A
Crash1) on PCM-highway A (line DXA) 0: 1: No crash detected Crash detected (bad programming in CR5-registers)
CRSH_B
Crash on PCM-highway B (line DXB) 0: 1: No crash detected Crash detected (bad programming in CR5-registers)
CHCLK2
Enables Chopper Clock Output to pin CHCLK2 0 0: 0 1: 1 0: 1 1: pin CHCLK2 is set to 1 A 512 kHz signal is fed to pin CHCLK2 A 256 kHz signal is fed to pin CHCLK2 A 16384 kHz signal (internal masterclock) is fed to pin CHCLK2 (at least one of the four channels has to be set to `POWER UP')
VERSION
1)
This two bit field identifies the actual chip version, is `00' for Version 1.1, and `01' for Version 1.2
A crash occurs, if 2 or more channels are programed to transmit (talk) in the same time slot on the same highway. In this case the crash-bit will be set, and transmission will be disabled for all affected channels.
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46
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Programming the SICOFI(R)-4-C 3.5.7 XR6 Extended Register 6
This register configures the operation of the PCM-interface Bit 7 C-MODE C-MODE X-S R-S DRV_0 Shift 0 PCM-OFFSET
Defines the CLK-Mode for the PCM-interface C-Mode = 0: C-Mode = 1: Single clocking is used Double clocking is used
X-S
Transmit Slope X-S = 0: X-S = 1: Transmission starts with rising edge Transmission starts with falling edge
R-S
Receive Slope R-S= 0: R-S= 1: Data is sampled with falling edge of PCLK Data is sampled with rising edge of PCLK
DRV_0
Driving Mode for Bit 0 (only available with single clocking mode) DRV_0 = 0: DRV_0 = 1: Bit 0 is driven the whole PCLK-period Bit 0 is driven during the first half of the PCLK-period only
Shift
Shifts the access to DXA/B and DRA/B for one PCLK-period (only available with double clocking mode) Shift = 0: Shift = 1: No shift takes place Access to DXA/B and DRA/B is shifted for one PCLK-per.
PCM-OFFSET
Offset in number of data-clock periods added to Time slot 0 0 0: 0 0 1: ... 111 Seven data clock periods are added No offset is added One data clock period is added
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47
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Programming the SICOFI(R)-4-C 3.5.8 XR7 Extended Register 7
This register contains the 8-bit offset value for the level metering function Bit 7 OF7 OF6 OF5 OF4 OF3 OF2 OF1 0 OF0
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48
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Programming the SICOFI(R)-4-C 3.5.9 Setting of Slopes in Register XR6
Transmit Slope FSC Receive Slope Single Clock Mode 76543210 00000000 XR6: 76543210 00100000 76543210 01000000 76543210 01100000
PCLK
Bit 7 Time-Slot 0 Double Clock Mode 76543210 XR6: 10000000 76543210 10100000 76543210 11000000 76543210 11100000
ITD09610
PCLK
Figure 13
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49
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Programming the SICOFI(R)-4-C 3.6 The Signaling Interface
The C-SICOFI-4 signaling interface is made up of 2 input pins (SIx_0, SIx_1), two output pins (SOx_0, SOx_1) and three bi-directional programmable pins (SBx_0, SBx_1, SBx_2) per channel. Additional two interrupt pins (INT12, INT34) are provided. If one of the input pins for channel 1 or 2, or one of the bi-directional pins for channel 1 and 2 (if programmed as inputs) changes, and being stable for the debounce time specified in Register XR4, INT12 will go from `0' to `1'. This interrupt is cleared if the appropriate registers (XR0, XR1 and XR3) are read via the serial C-interface. Pin INT34 provides the same functionality for channel 3 and 4. For special purposes two additional output signals are provided by the PEB 2466. CHCLK1 (see also register XR4) will provide a programmable time period of 2 to 28 ms. CHCLK2 will provide 3 different frequencies (256 kHz, 512 kHz or 16384 kHz). Both signals are only available if a valid signal is applied to the MCLK-pin. 3.6.1 Operating Modes
Figure 14
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PEB 2466
Programming the SICOFI(R)-4-C RESET (Basic Setting Mode) Upon initial application of VDD or resetting pin RESET to `0' during operation, or by software-reset (see XOP command), the SICOFI-4-C enters a basic setting mode. Basic setting means, that the SICOFI-4-C configuration registers CR0... CR6 and XR0... XR7 are initialized to `0' for all channels. All programmable filters are disabled, all programmable command/indication pins are inputs. The two tone generators as well as any testmodes are disabled. There is no persistence checking. Receive signaling registers are cleared. DOUT-pin is in high impedance state, the analog outputs and the signaling outputs are forced to ground. CR0.. CR6 XR0.. XR7 Coefficient-RAM Command Stack DIN-input DOUT-output VOUT1,2,3,4 SBx_y SOx_y 00H 00H Old value Cleared Ignored High impedance GNDA1,2,3,4 Input GNDD
If any voltage is applied to any input-pin before initial application of VDD, the SICOFI-4-C may not enter the basic setting mode. In this case it is necessary to reset the SICOFI-4-C or to initialize the SICOFI-4-C configuration registers to `0'. The SICOFI-4-C leaves this mode automatically after the RESET-pin is released. Standby Mode After releasing the RESET-pin, (RESET-state), the SICOFI-4-C will enter the Standby mode. The SICOFI-4-C is forced to standby mode with the PU-bit set to `0' in the CR1-register (POWERDOWN). All 4 channels must be programmed separately. During standby mode the serial SICOFI-4-C -Controller interface is ready to receive and transmit commands and data. Received voice data on DRA, DRB-pin will be ignored. SICOFI-4-C configuration registers and Coefficient-RAM can be loaded and read back in this mode. Data on signaling input pins can be read via the -Controller interface. DXA, DXB VOUT1, 2, 3, 4 High `Z' GNDA1, 2, 3, 4
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PEB 2466
Programming the SICOFI(R)-4-C Operating Mode The operating mode for any of the four channels is entered upon recognition of a PU-bit set to `1' in a CR1-register for the specific channel. 3.6.2 Programmable Filters
Based on an advanced digital filter concept, the PEB 2466 provides excellent transmission performance and high flexibility. The new filter concept leads to a maximum independence between the different filter blocks. Impedance Matching Filter * Realization by 3 different loops - 4 MHz: - 128 kHz: - 64 kHz: Multiplication by a constant Wave Digital Filter (IIR) Improves low frequency response FIR-Filter For fine-tuning * Improved stability behavior of feedback loops * Real part of termination impedance positive under all conditions * Improved overflow performance for transients * Return loss better 30 dB Transhybrid Balancing (TH) Filter * New concept: 2 loops at 16 kHz * Flexible realization allows optimization of wide impedance range * Consists of a fixed and a programmable part - 2nd order Wave Digital Filter (IIR) Improves low frequency response - 7-TAP FIR-Filter For fine-tuning * Trans-Hybrid-Loss better 30 dB (typically better 40 dB, device only) * Adaptation to different lines by: - Easy selection between four different downloaded coefficient sets (84 bit) (106 bit) (48 bit) (12 bit) (60 bit)
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Programming the SICOFI(R)-4-C Filters for Frequency Response Correction * For line equalization and compensation of attenuation distortion * Improvement of Group-Delay-Distortion by using minimum phase filters (instead of linear phase filters) * FRR filter for correction of receive path distortion - 5 TAP programmable FIR filter operating at 8 kHz * FRX filter for correction of transmit path distortion - 5 TAP programmable FIR filter operating at 8 kHz * Frequency response better 0.1 dB Amplification/Attenuation -Filters AX1, AX2, AR1, AR2 * Improved level adjustment for transmit and receive * Two separate filters at each direction for - Improved trans-hybrid balancing - Optimal adjustment of digital dynamic range - Gain adjustments independent of TH-filter Amplification/Attenuation Receive (AR1, AR2)-Filter Step size for AR-Filter range 3 .. - 14 dB: range - 14 .. - 24 Amplification/Attenuation Transmit (AX1, AX2)-Filter Step size for AX-Filter range - 3 .. 14 dB: range 14 .. 24 dB: 3.6.3 QSICOS Software step size 0.02 .. 0.05 dB step size 0.5 dB step size 0.02 .. 0.05 dB step size 0.5 dB (60 bit) (60 bit)
The QSICOS-software has been developed to help to obtain an optimized set of coefficients both quickly and easily. The QSICOS program runs on any PC with at least 575 Kbytes of memory. This also requires MS-DOS Version 5.0 or higher, as well as extended memory.
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Programming the SICOFI(R)-4-C
Calculation-Controlfile Country-Spec RD[dB]
Simulation (PSPICE)
f [Hz]
Automatic K-Param Extraction
~
Line Interface
Line Interface
~
K-Parameter InterfaceFile
K11 = (Z IN - Z g ) / (Z IN + Z g )
K12 = 2 * V1 / V3
QSICOS
Software for Filter-Coefficients-Optimization
SICOFI Coefficients File
R
~
Line Interface
Line Interface
~
ITD09611
K21 = V2 / Vg
K22 = V2 / V3
Figure 15 QSICOS Supports: * Calculation of Coefficients for the - Impedance Filter (IM) for return loss calculation (please note that the IM filter coefficients are different for the PEB 2466 and for the PEB 2465. QSICOS calculates the programming bytes for the SICOFI-4 IOM version PEB 2465. These bytes have to be converted with an additional tool to get the required PEB 2466 programming bytes. The conversion tool QSUCCONV.EXE is part of the QSICOS software package.) - FRR and FRX-filters for frequency response in receive and transmit path - AR1, AR2 and AX1, AX2-filter for level adjustment in receive and transmit path - Trans Hybrid Balancing Filter (TH) and - two programmable tone generators (TG 1 and TG 2) * Simulation of the PEB 2466 and SLIC System with fixed filter coefficients allows simulations of tolerances which may be caused e.g. by discrete external components. * Graphical Output of Transfer Functions to the Screen for - Return Loss - Frequency responses in receive and transmit path - Transhybrid Loss * Calculation of the PEB 2466 and SLIC system Stability. The IM-filter of the PEB 2466 adjust the total system impedance by making a feedback loop. Because the line is also a part of the total system, a very robust method has to used to avoid oscillations and to ensure system stability. The input impedance of the PEB 2466 and SLIC combination is calculated. If the real part of the system input impedance is positive, the total system stability can be guaranteed.
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PEB 2466
Transmission Characteristics 4 Transmission Characteristics
The figures in this specification are based on the subscriber-line board requirements. The proper adjustment of the programmable filters (transhybrid balancing, impedance matching, frequency-response correction) requires a complete knowledge of the C-SICOFI-4's analog environment. Unless otherwise stated, the transmission characteristics are guaranteed within the test conditions. Test Conditions
TA = 0 C to 70 C; VDD = 5 V 5%; GNDA1..4 = GNDD = 0 V RL1) > 300 ; CL < 50 pF; H(IM) = H(TH) = 0; H(R1) = H(FRX) = H(FRR) = 1;
HPR and HPX enabled; AR2)= 0 to - 9 dB AX3)= 0 to 9 dB for A-Law, 0 to 7 dB for -Law f = 1014 Hz; 0 dBm0; A-Law or -Law; AGX = 0 dB, 6.02 dB, AGR = 0 dB, - 6.02dB; A-Law A 0 dBm0 signal is equivalent to 1.095 Vrms. A + 3.14 dBm0 signal is equivalent to 1.57 Vrms which corresponds to the overload point of 2.223 V. When the gain in the receive path is set at 0 dB, an 1014 Hz PCM sinewave input with a level 0 dBm0 will correspond to a voltage of 1.095 Vrms at the analog output. When the gain in the transmit path is set at 0 dB, an 1014 Hz sine wave signal with a voltage of 1.095Vrms A-Law will correspond to a level of 0 dBm0 at the PCM output. -Law In transmit direction for -law an additional gain of 1.94 dB is implemented automatically, in the companding block (CMP). This additional gain has to be considered at all gain calculations, and reduces possible AX-gain from 9 dB (with A-Law) to 7 dB (with -Law) A 0 dBm04) signal is equivalent to 1.0906 Vrms. A + 3.17 dBm0 signal is equivalent to 1.57 Vrms which corresponds to the overload point of 2.223 V. When the gain in the receive path is set at 0 dB, an 1014 Hz PCM sinewave input with a level 0 dBm0 will correspond to a voltage of 1.0906 Vrms at the analog output. When the gain in the transmit path is set at 0 dB, an 1014 Hz sine wave signal with a voltage of 1.0906 Vrms will correspond to a level of 1.94 dBm0 at the PCM output.
1) 2) 3) 4)
RL, CL forms the load on VOUT
Consider, in a complete system, AR = AR1 + AR2 + FRR + R1 Consider, in a complete system, AX = AX1 + AX2 + FRX The absolute power level in decibels referred to (a point of zero relative level) the PCM interface levels.
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Transmission Characteristics Transmission Characteristics Parameter Gain absolute (AGX = AGR = 0) TA= 25 C; VDD = 5 V TA = 0 - 70 C; VDD = 5 V 5% Gain absolute (AGX = 6.02 dB, AGR = - 6.02 dB) TA = 25C; VDD = 5 V TA = 0-70C; VDD = 5 V 5% Harmonic distortion, 0 dBm0; f = 1000 Hz; 2nd, 3rd order Intermodulation1) Symbol min. Limit Values typ. max. Unit
G
- 0.15 0.10 + 0.15 dB - 0.25 + 0.25 dB
G
- 0.15 0.10 + 0.15 dB - 0.25 + 0.25 dB
HD IMD IMD
- 50
- 44 - 46 - 56
dB dB dB dB
R2 R3
Crosstalk 0 dBm0; f = 200 Hz to 3400 Hz any CT combination of direction and channel Idle channel noise, Transmit, A-law, psophometric (VIN = 0 V) Transmit, -law, C-message (VIN = 0 V) Transmit, -law, C-message (VIN = 0V) Receive, A-law, psophometric (idle code + 0) Receive, -law, C-message (idle code + 0) Receive, -law, C-message (idle code + 0)
1)
- 85
- 80
NTP NTC NTC NRP NRC NRC
- 85 5 5
- 67.4 17.5 17.5 - 78.0 12.0 12.0
dBm0p dBmc dBrnC0 dBm0p dBmc dBrnC0
Using equal-level, 4-tone method (EIA) at a composite level of - 13 dBm0 with frequencies in the range between 300 Hz and 3400 Hz.
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Transmission Characteristics 4.1 Frequency Response
Figure 16 Receive: Reference Frequency 1014 Hz, Input Signal Level 0 dBm0
Figure 17 Transmit: Reference Frequency 1014 Hz, Input Signal Level 0 dBm0
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Transmission Characteristics 4.2 Group Delay
Maximum delays when the SICOFI-4-C is operating with H(TH) = H(IM) = 0 and H(FRR) = H(FRX) = 1 including delay through A/D- and D/A converters. Specific filter programming may cause additional group delays. Group delay deviations stay within the limits in the figures below. Group Delay Absolute Values: Input signal level 0 dBm0 Parameter Transmit delay Receive delay Symbol min. Limit Values typ. max. 300. 250 s s Unit Reference
DXA DRA
Figure 18 Group Delay Distortion Transmit: Input Signal Level 0 dBm0
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Transmission Characteristics
Figure 19 Group Delay Distortion Receive: Input Signal Level 0 dBm0 1)
1)
HPR is switched on: reference point is at tGmin HPR is switched off: reference is at 1.5 kHz
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Transmission Characteristics 4.3 Out-of-Band Signals at Analog Input
With an 0 dBm0 out-of-band sine wave signal with frequency f (<<100 Hz or 3.4 kHz to 100 kHz) applied to the analog input, the level of any resulting frequency component at the digital output will stay at least X dB below a 0 dBm0, 1 kHz sine wave reference signal at the analog input.1)
4000 - f 3.4 ... 4.0 kHz: X = - 14 sin -------------------- - 1 1200 4000 - f 7 * 4,0 ... 4.6 kHz: X = - 18 sin -------------------- - -- 1200 9
Figure 20
1)
Poles at 12 kHz 150 Hz and 16 kHz 150 Hz are provided
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Transmission Characteristics 4.4 Out-of-Band Signals at Analog Output
With a 0 dBm0 sine wave with frequency f (300 Hz to 3.99 kHz) applied to the digital input, the level of any resulting out-of-band signal at the analog output will stay at least X dB below a 0 dBm0, 1 kHz sine wave reference signal at the analog output.
4000 - f 3.4 ... 4.6 kHz: X = - 14 sin -------------------- - 1 1200
Figure 21
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Transmission Characteristics 4.5 Out of Band Idle Channel Noise at Analog Output
With an idle code applied to the digital input, the level of any resulting out-of-band power spectral density (measured with 3 kHz bandwidth) at the analog output, will be not greater than the limit curve shown in the figure below.
Figure 22
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Transmission Characteristics 4.6 Overload Compression
Figure 23 -Law, Transmit: measured with sine wave f = 1014 Hz.
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Transmission Characteristics 4.7 Gain Tracking (receive or transmit)
The gain deviations stay within the limits in the figures below.
Figure 24 Gain Tracking: (measured with sine wave f = 1014 Hz, reference level is 0 dBm0)
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Transmission Characteristics 4.8 Total Distortion
The signal to distortion ratio exceeds the limits in the following figure. 4.8.1 Total Distortion Measured with Sine Wave
Figure 25 Receive or Transmit: measured with sine wave f = 1014 Hz. (C-message weighted for -law, psophometricaly weighted for A-law)
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Transmission Characteristics 4.8.2 Total Distortion Measured with Noise According to CCITT
Figure 26 Receive
Figure 27 Transmit
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Transmission Characteristics 4.9 Single Frequency Distortion
An input signal with its frequency swept between 0.3 to 3 kHz for the receive path, or 0 to 12 kHz for the transmit path, any generated output signal with other frequency than the input frequency will stay 28 dB below the maximum input level of 0 dBM0. Receive Frequency 300 Hz to 3.4 kHz 4.10 Max Input Level 0 dBm0 Frequency 0 to 12 kHz Transmit Max. Input Level 0 dBm0
Transhybrid Loss
The quality of Transhybrid-Balancing is very sensitive to deviations in gain and group delay - deviations inherent to the SICOFI-4-C A/D- and D/A-converters as well as to all external components used on a line card (SLIC, OP's etc.) Measurement of SICOFI-4-C Transhybrid-Loss: A 0 dBm0 sine wave signal and a frequency in the range between 300-3400 Hz is applied to the digital input. The resulting analog output signal at pin VOUT is directly connected to VIN, e.g. with the SICOFI-4-C testmode "Digital Loop Back via Analog Port". The programmable filters FRR, AR, FRX, AX and IM are disabled, the balancing filter TH is enabled with coefficients optimized for this configuration (VOUT = VIN). The resulting echo measured at the digital output is at least X dB below the level of the digital input signal as shown in the table below. (Filter coefficients will be provided) Parameter Transhybrid Loss at 300 Hz Symbol Limit Values Unit Test Condition min. typ. 40 45 40 35 35 dB dB dB dB dB 27 33 29 27 27
THL300 Transhybrid Loss at 500 Hz THL500 Transhybrid Loss at 2500 Hz THL2500 Transhybrid Loss at 3000 Hz THL3000 Transhybrid Loss at 3400 Hz THL3400
TA = 25 C; VDD = 5 V; TA = 25 C; VDD = 5 V; TA = 25 C; VDD = 5V; TA = 25 C; VDD = 5V; TA = 25 C; VDD = 5 V
The listed values for THL correspond to a typical variation of the signal amplitude and delay in the analog blocks. amplitude delay = typ. 0.15 dB = typ 0.5 s
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Electrical Characteristics 5 Electrical Characteristics
Absolute Maximum Ratings Parameter Symbol Limit Values Unit Test Condition min. max. 7.0 0.6 0.3 5.3 5.3 0.3 10 V V V V V V mA - 0.3 - 0.6 - 5.3 - 0.3 - 0.3 - 5.3
VDD referred to GNDD
GNDA to GNDD Analog input and output voltage Referred to VDD = 5 V; Referred to GNDA = 0 V All digital input voltages Referred to GNDD = 0 V; (VDD = 5V) Referred to VDD = 5 V; (GNDD = 0 V) DC input and output current at any input or output pin (free from latch-up) Storage temperature Ambient temperature under bias Power dissipation (package)
TSTG TA PD
- 60 - 10
125 80 1
C C W
Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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Electrical Characteristics Operating Range TA = 0 to 70 C; VDD = 5 V 5%; GNDD = 0 V; GNDA = 0 V Parameter Symbol Limit Values min. typ. max. 1.0 40 mA mA Ripple: 0 to 150 kHz, 70 mVrms Measured: 300 Hz to 3.4 kHz Measured: at f: = 3.4 to 150 kHz 1 channel 2 channels 3 channels 4 channels Unit Test Condition
VDD supply current standby Operating (4 channels)
Power supply rejection Of either supply/direction Receive VDD target value Power dissipation standby1) Power dissipation operating Power dissipation operating Power dissipation operating Power dissipation operating
1)
IDIN
0.5 26
PSRR
30 14 dB dB 2.5 100 110 120 130 6 175 200 225 250 mW mW mW mW mW
PDS PDo1 PDo2 PDo3 PDo4
Power dissipation values are target values
Note: In the operating range the functions given in the circuit description are fulfilled.
Digital Interface TA = 0 to 70 C; VDD = 5 V 5%; GNDD = 0 V; GNDA = 0 V Parameter Low-input voltage High-input voltage Low-output voltage High-output voltage Input leakage current Symbol Limit Values Unit min. max. 0.8 0.45 4.4 1 V V V V A - 0.3 2.0 Test Condition
VIL VIH VOL VOH VIL
I0 = - 5mA I0 = 5 mA - 0.3 VIN VDD
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Electrical Characteristics Analog Interface TA = 0 to 70 C; VDD = 5 V 5%; GNDD = 0 V; GNDA = 0 V Parameter Analog input resistance Analog output resistance Analog output load Input leakage current Input offset voltage Output offset voltage Input voltage range (AC) Symbol min. Limit Values typ. 270 max. 380 0.25 300 50 0.1 1.0 50 50 k pF A mV mV 0 VIN VDD 160 Unit Test Condition
Ri RO RL CL IIL VIO VOO VIN
2.223 V
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Electrical Characteristics 5.1 Coupling Capacitors at the Analog Interface
In Transmit direction, a 39 nF capacitor has to be connected to VIN-pins. To fulfil the frequency response requirement in Receive direction, the value of the coupling capacitor (Cext1) needed, depends on the input resistance of the SLIC-circuitry (equals the Analog-Output-Load: RLoad).
Figure 28 5.2 Reset Timing
To reset the SICOFI-4-C to basic setting mode, negative pulses applied to pin RESET have to be lower than 1.2 V (TTL-Schmitt-Trigger Input) and have to be longer than 3 s. Spikes shorter than 1 s will be ignored.
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Electrical Characteristics 5.3 PCM-Interface Timing
t PCLK
PCLK 50%
t PCLKh
t FSC t FSC_S
FSC
t FSC_H
t DR_S t DR_H
DRA/B
t dDX
DXA/B
t dDXhz
High Imp.
t dTCon
TCA/B
t dTCoff
ITD07276
Figure 29 Single Clocking Mode Parameter Period of PCLK PCLK high time Period FSC FSC setup time FSC hold time DRA/B setup time DRA/B hold time DXA/B delay time 1) DXA/B delay time to high Z TCA/B delay time on TCA/B delay time off
1)
Symbol min.
Limit Values typ. max. 1/128 1/8192
Unit ms s s ns ns ns ns ns ns ns ns
tPCLK tPCLKh tFSC tFSC_s tFSC_h tDR_s tDR_h tdDX tdDXhz tdTCon tdTCoff
tPCLK/2
125 10 50 (tPCLK - t PCLKh) (tPCLK - tPCLKh) + 10 + 50 10 10 25 25 25 25 50 50 50 (@ 200 pF) 50 50 100
All delay times are made up by two components: an intrinsic time (min-time), caused by internal processings, and a second component caused by external circuitry (C-load)
Semiconductor Group
72
02.97
PEB 2466
Electrical Characteristics
t PCLK
PCLK 50%
t PCLKh
t FSC t FSC_S
FSC
t FSC_H
t DR_S t DR_H
DRA/B
t dDX
DXA/B
t dDXhz
High Imp.
t dTCon
TCA/B
t dDTCoff
ITD07277
Figure 30 Double Clocking Mode Parameter Period of PCLK PCLK high time Period FSC FSC setup time FSC hold time DRA/B setup time DRA/B hold time DXA/B delay time 1) DXA/B delay time to high Z TCA/B delay time on TCA/B delay time off
1)
Symbol min.
Limit Values typ. max. 1/256 1/8192
Unit ms s s ns ns ns ns ns ns ns ns
tPCLK tPCLKh tFSC tFSC_s tFSC_h tDR_s tDR_h tdDX tdDXhz tdTCon tdTCoff
tPCLK/2
125 10 2 x (tPCLK - tPCLKh) + 10 10 10 25 25 25 25 50 2 x (tPCLK - tPCLKh) + 50 50 50 50 (@200 pF) 50 50 100
All delay times are made up by two components: an intrinsic time (min-time), caused by internal processings, and a second component caused by external circuitry (C-load)
Semiconductor Group
73
02.97
PEB 2466
Electrical Characteristics 5.4 -Controller Interface Timing
t DCLK
DCLK 50%
t DCLKh
t CS_S
CS
t CS_h
t DIN_S t DIN_H
DIN
t dDOUT
DOUT
t dDOUThz
High Imp.
ITD07278
Figure 31
Parameter Period of DCLK
Symbol min. 1/8192
Limit Values typ. max.
Unit ms
tDCLK tDCLKh DCLK high time tCS_s CS setup time tCS_h CS hold time tDIN_s DIN setup time tDIN_h DIN hold time tdDOUT DOUT delay time 1) DOUT delay time to high Z tdDOUThz
1)
tDCLK/2
10 30 10 10 30 30 50 50 50 50 100 100
s ns ns ns ns ns ns
All delay times are made up by two components: an intrinsic time (min-time), caused by internal processings, and a second component caused by external circuitry (C-load)
Semiconductor Group
74
02.97
PEB 2466
Electrical Characteristics 5.5 5.6 Signaling Interface From the C-interface to the SO/SB-pins (data downstream)
Parameter SO/SB delay time 1) SB to `Z' - time SB to `drive'-time
1)
Symbol min.
Limit Values typ. 100 100 100 max. 30 40 40
Unit ns ns ns
tdSout tdSBZ tdSBD
All delay times are made up by two components: an intrinsic time (min-time), caused by internal processings, and a second component caused by external circuitry (C-load)
5.7
From the SI/SB-pins to the C-interface (data upstream)
There is no way specifying the time when data applied to SI-pins (and SB-pins if programmed as signaling input pins) is sampled by the PEB 2466. The time only depends on internal signals (16 MHz masterclock, and status of various counters), and there is no link to a low frequency external signal.
Semiconductor Group
75
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PEB 2466
Package Outlines 6 Package Outlines P-MQFP-64 (Plastic Metric Quad Flat Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 76
Dimensions in mm 02.97
GPM05250
PEB 2466
Appendix 7 7.1 Appendix Level Metering Function
This function allows a selftest of the SICOFI-4 and also of the SLIC circuitry connected to the analog interface. The receive path has to be stimulated with a sine wave applied to the digital input, or generated by one of the internal tone generators. By closing an internal or external (via the SLIC) loop to the transmit path, the outgoing signal is compared with a programmable offset. (For further information, an application-note describing the calculation of the offset value and the sensitivity, is available)
Semiconductor Group
77
02.97
PEB 2466
Appendix
Figure 32
Semiconductor Group 78 02.97
PEB 2466
Appendix 7.2 Programming the SICOFI(R)-4-C Tone Generators
Two independent Tone Generators are available per channel. Switching on/off the Tone Generators is done by a SOP-Command for CR1-register. The frequencies are programmed via a COP-Command, followed by the appropriate byte-sequence. When one or both tone-generators are switched on, the voice signal is switched off, if V+T=0 (CR2) for the selected voice channel. To make the generated signal sufficient for DTMF, a programmable bandpass-filter is included. The default frequency for both tone generators is 1000 Hz. The QSICOS-program contains a program for generating coefficients for variable frequencies. Byte sequences for programming both the tone generators and the bandpass-filters: Table 2 Frequency 697 Hz 800 Hz 950 Hz 1008 Hz 2000 Hz
1)
Command 0C/0D 1) 0C/0D 1) 0C/0D 1) 0C/0D 1) 0C/0D 1)
Byte 1 0A 12 1C 1A 00
Byte 2 33 D6 F0 AE 80
Byte 3 5A 5A 5C 57 50
Byte 4 2C C0 C0 70 09
0C is used for programming Tone Generator 1, in channel 1 0D is used for programming Tone Generator 2, in channel 1
The resulting signal amplitude can be set by transmitting the AR1 and AR2 filters. By switching a `digital loop' the generated sine-wave signal can be fed to the transmit path.
Semiconductor Group
79
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PEB 2466
Proposed Test Circuit 8 Proposed Test Circuit
PC
Printer-Port (25 pin SUB-D plug)
GND CS DCLK DIN DOUT 6, 7, 8, 9 2 3 4 5 GNDA3 GNDA4
(9-pol. SUB-D plug)
SB3_2
SB3_0
SO3_0
SO4_0
SB4_0
SB4_2
SI4_0
SB3_1
SO3_1
SO4_1
SB4_1
VOUT4
10 F *
VIN4
GNDA4
INT34
SI4_1
1 F
1 64 63
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 CS 17 18 19 20 21 22 23
GNDA4 GNDA3
GNDA4 GNDA3
DCLK 1 = SI3_1 2 = SI3_0 16 = CHCLK2 DIN DOUT GNDD MCLK RESET M0381 R SICOFI 4 - C
VDDA34
VDDA34
VIN4 VDDA34 10 F VOUT3
1 F *
62 61 60 59
VOUT4 VDDA34 VOUT3
GNDA3
MCLK
VIN3
58 57
VIN3 VDDREF VREF VIN2
GNDA2
* 220 nF 1 F
VDDD 24
* TCA DXA DRA TCB DXB 25 26 27 28 29 30 31 32 GNDA2 GNDA1 1-10 F
+
VDDD
56 55 54
VIN2
10 F *
GNDD
VOUT2
53 52 51 * 50
VOUT2 VDDA12 VOUT1
GNDA1
SO2_1 SO2_0 SO1_0 SO1_1 SB2_2 SB2_1 SB2_0 SB1_0 SB1_1 SB1_2 INT12 SI1_0 SI1_1
VDDA12
VOUT1
10 F
GNDA2 GNDA1
48 = SI2_1 47 = SI2_0
DRB 33 = CHCLK1 FSC PCLK 33
1 F
VDDA12 VDDREF
VDDA12 VDDREF
VIN1
49
VIN1
48 47
46
45
44
43
42
41
40
39
38
37
36
35
34
VDDREF
GNDA2 GNDA1
FSC
DR
220 nF an VREF as near as possible to the pin = Banana-Bush = BNC-Bush
* Filter-Cs: 100 nF SMD as near as possible to the pin + 2.2 F Ta-Cap.
All resistors: app. 680 k
= Test-Point
PCLK
22
61
21
PCM4
ITS09614
Figure 33
Semiconductor Group 80 02.97
DX
20
PEB 2466
Guidelines for Board-Design 9 9.1 Guidelines for Board-Design Board Layout Recommendation
Keep in mind that inside the SICOFI-4-C all the different VDD-supplies are connected via the substrate of the chip, and the areas connected to different grounds are separated on chip. a) Separate all digital supply lines from analog supply lines as much as possible. b) Use a separate GND-connection for the capacitor which is filtering the reference voltage (220 nF ceramic-capacitor at VREF). c) Don't use a common ground-plane under the SICOFI-4-C. d) Use a large ground-plane (distant from the SICOFI-4-C) and use three single ground lines for connecting the SICOFI-4-C: one common analog ground, one digital ground, and a third for the 220 nF capacitor connected to VREF. 9.2 Filter Capacitors
a) To achieve a good filtering for the high frequency band, place SMD ceramic-capacitors with 100 nF from VDDA12, VDDA32 and VDDREF to GNDA. b) One 100 nF SMD ceramic-capacitor is needed to filter the digital supply (VDDD to GNDD). c) Place all filter capacitors as close as possible to the SICOFI-4-C (most important!!!). d) Use one central Tantalum-capacitor with about 1 F to 10 F to block VDD to GND.
Semiconductor Group
81
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PEB 2466
Guidelines for Board-Design 9.3 Example of a PEB 2466-board
VDDD
Ceramic 100 nF GNDD
VDD
1-10 F Tantal
32 31 30 29 28 27 26 25 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
GNDA1
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 62 63 64
GNDA4
VDD
VDD
PEB 2466 H
VDD
VDDREF VDDA12 VREF
VDD
VDDA34
GNDA3
49 50 51
53 54 55 56
GNDA2 220 nF
58 59 60
GND
100 nF Ceramic
100 nF Ceramic
100 nF Ceramic
ITS09615
Figure 34
Semiconductor Group
82
02.97

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